module mem_wb(
    input clk,
    input reset,
    input [5:0] stall,

    input i_write_to_regfile,//回id
    input i_mem_to_regfile,
    input [4:0] i_reg_addr,//回id
    input [63:0] i_alu_data,
    input [63:0] i_mem_data,
    input [63:0] i_pc,
    input [31:0] i_inst,
    input [63:0] i_badvaddr,
    input [63:0] i_excode,
    input i_except_ena,
    input flush,
    input i_ret,
    input i_inst_r_valid,
    input i_mtime_int,
    input i_csr_write_ena,
    input [63:0] i_csr_data_res,
    input [11:0] i_csr,

    output reg o_write_to_regfile,
    output reg o_mem_to_regfile,
    output reg [4:0] o_reg_addr,
    output reg [63:0] o_alu_data,
    output reg [63:0] o_mem_data,
    output reg [63:0] o_pc,
    output reg [31:0] o_inst,
    output reg [63:0] o_badvaddr,
    output reg [63:0] o_excode,
    output reg o_except_ena,
    output reg o_ret,
    output reg o_inst_r_valid,
    output reg o_mtime_int,
    output reg o_csr_write_ena,
    output reg [63:0] o_csr_data_res,
    output reg [11:0] o_csr
);

    always @(posedge clk) begin
        if(reset) begin
            o_write_to_regfile <= 1'b0;
            o_mem_to_regfile <= 1'b0;
            o_reg_addr <= 5'd0;
            o_alu_data <= 64'd0;
            o_mem_data <= 64'd0;
            o_badvaddr <= 64'd0;
            o_excode <= 64'd0;
            o_except_ena <= 1'b0;
            o_ret <= 1'b0;
            o_csr_data_res <= 64'd0;
            o_csr_write_ena <= 1'b0;
            o_csr <= 12'd0;
        end else if(flush) begin
            o_write_to_regfile <= 1'b0;
            o_mem_to_regfile <= 1'b0;
            o_reg_addr <= 5'd0;
            o_alu_data <= 64'd0;
            o_mem_data <= 64'd0;
            o_badvaddr <= 64'd0;
            o_excode <= 64'd0;
            o_except_ena <= 1'b0;
            o_ret <= 1'b0;
            o_csr_data_res <= 64'd0;
            o_csr_write_ena <= 1'b0;
            o_csr <= 12'd0;
        end else if(stall[4] == 1'b0 && stall[5] == 1'b0) begin
            o_write_to_regfile <= i_write_to_regfile;
            o_mem_to_regfile <= i_mem_to_regfile;
            o_reg_addr <= i_reg_addr;
            o_alu_data <= i_alu_data;
            o_mem_data <= i_mem_data;
            o_badvaddr <= i_badvaddr;
            o_excode <= i_excode;
            o_except_ena <= i_except_ena;
            o_ret <= i_ret;
            o_csr_data_res <= i_csr_data_res;
            o_csr_write_ena <= i_csr_write_ena;
            o_csr <= i_csr;
        end
    end

    always @(posedge clk) begin
        if(reset) begin
            o_pc <= 64'h0000000080000000;
            o_inst <= 32'd0;
            o_mtime_int <= 1'b0;
            o_inst_r_valid <= 1'b0;
        end else if(stall[4] == 1'b0 && stall[5] == 1'b0) begin
            o_pc <= i_pc;
            o_inst <= i_inst;
            o_mtime_int <= i_mtime_int;
            o_inst_r_valid <= i_inst_r_valid;
        end
    end
endmodule
